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1 features ? 20ns read, 10ns write maximum access times ? functionally compatible with traditional 512k x 32 sram devices ? cmos compatible input and output levels, three-state bidirectional data bus - i/o voltage 3.3 volt, 1.8 volt core ? operational environment: - total-dose: 100 krad(si) - sel immune: 111mev-cm 2 /mg - seu error rate = 6.0x10 -16 errors/bit-day assuming geosynchronous orbit, adam?s 90% worst environment, and 6600ns default scrub rate period (=97% sram availability) ? packaging options: - 68-lead ceramic quad flatpack (6.898 grams) ? standard microcircuit drawing 5962-06261 - qml q & v pending introduction the ut8er512k32 is a high-performance cmos static ram organized as 524,288 words by 32 bits. easy memory expansion is provided by active low and high chip enables (e1 , e2), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplishe d by driving chip enable one (e1 ) input low, chip enable tw o (e2) high and write enable (w ) input low. data on the 32 i/o pins (dq0 through dq31) is then written into the location specified on the address pins (a0 through a18). reading from the device is accomplished by taking chip enable one (e1 ) and output enable (g ) low while forcing write enable (w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 32 input/output pins (dq0 through dq31) are placed in a high impedance state when th e device is deselected (e1 high or e2 low), the outputs are disabled (g high), or during a write operation (e1 low, e2 high and w low). standard products ut8er512k32 monolithic 16m sram preliminary data sheet february, 2009 www.aeroflex.com/memories figure 1. ut8er512k32 sram block diagram memory array 512k x 32 pre-charge circuit column select row select a3 a4 a6 a7 a8 a9 a17 a18 data control i/o circuit a10 a11 a12 a13 a14 a15 dq(31) to dq(0) e1 w e2 g a2 a16 read/write circuit edac a5 a1 a0 busy , scrub mbe
2 ut8er512k32 master or slave options to reduce the bit error rates, the ut8er512k32 employs an embedded edac (error detectio n and correction) with user programmable auto scrubbing options. the ut8er512k32 device automatically co rrects single bit word errors in event of an upset. during a read operation, if a multiple bit error occurs in a word, the ut8er512k32 asserts the mbe (multiple bit error) output to notify the host. the ut8er512k32 is offered in two options: master (ut8er512k32m) or slave (ut8 er512k32s). the master is a full function device which features user defined autonomous edac scrubbing options. the slave device employs a scrub on demand feature. the ut8er512k32m (master) and ut8er512k32s (slave) device pins scrub and busy are physically different. the scrub pin is an output on master devices, but an input on slave devices. the master scrub pin asserts low when a scrub cycle initiates, and can be us ed to demand scrub cycles from multiple slave units when connected to the scrub input of slave(s). the busy pin is an output for the mast er device and can be used to generate wait states by the memory controller. the busy pin is a no connect (nc) for slave units. note: pin 31 on the ut8er512k32s (slave) is a no connect (nc). pin descriptions device operation the ut8er512k32 has four control inputs called enable 1 (e1 ), enable 2 (e2), write enable (w ), and output enable (g ); 19 address inputs, a(18:0); and 32 bidirectional data lines, dq(31:0). e1 and e2 device enables control device selection, active, and standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active va lue, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write operat ions. during a read cycle, g must be asserted to enable the outputs. table 1. sram device control operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 v ss a0 a1 a2 a3 a4 a5 a17 v ss a18 w a6 a7 a8 a9 a10 v dd1 v dd1 a11 a12 a13 a14 a15 a16 e1 g e2 v dd2 v ss scrub busy mbe v dd2 v ss dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 figure 2. 20ns sram pinout (68) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 pins type description a(18:0) i address dq(31:0) bi data input/output e1 i enable (active low) e2 i enable (active high) w i write enable g i output enable v dd1 ppower (1.8) v dd2 ppower (3.3v) v ss pground mbe bi multiple bit error scrub i slave scrub input scrub omaster scrub output busy nc slave no connect busy o master wait state control g w e2 e1 i/o mode mode x x x h dq(31:0) 3-state standby x x l x dq(31:0) 3-state standby l h h l dq(31:0) data out word read h h h l dq(31:0) all 3-state word read 2 x l h l dq(31:0) data in word write
3 table 2. edac control pin operation truth table notes: 1. ?x? is defined as a ?don?t care? condition 2. busy signal is a "nc" for ut8er512k32s slave device and is an "x" don?t care. read cycle a combination of w and e2 greater than v ih (min) and e1 and g less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while e1 and e2 are asserted, g is asserted, and w is deasserted. valid data appears on data outputs dq(31:0) after the specified t av q v is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the minimum time between valid address changes is specified by the read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by the latter of either e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the 32-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(31:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv (reference figure 3b) have not been satisfied. sram edac status indications during a read cycle, if mbe is low, the data is good. if mbe is high the data is corrupted (reference table 2). write cycle a combination of w and e1 less than v il (max), and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high- impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-c ontrolled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pu lse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 and e2. to avoid bus contention t wlqz must be satisfied before data is applied to the 32 bidirectional pins dq(31:0) unless the outputs have been previously placed in high impedance state by deasserting g . write cycle 2, the chip enable-c ontrolled access in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have been previous ly placed in the high-impedance state by g , the user must wait t wlqz before applying data to the thirty-two bidirectional pins dq(31:0) to avoid bus contention. control register write/read cycles configuration options can be selected by writing to the control register. the configuration table (table 4) details the programming options. the control register is accessed by applying a series of values to the address bus as shown in figure 6a. the contents of the control register are written following the fifth address. the contents of the address bus are written to the control register if bit 9 is zero. th e contents of the control register are output to the data bus if bit 9 is one. note: mbe must be driven high by the user for both a write or a read of the control register. memory scrubbing/cycle stealing the ut8er512k32 sram uses architectural improvements and embedded error detection and correction to maintain unsurpassed levels of error prot ection. this is accomplished by what aeroflex refers to as cycle stealing. to minimize the system design impact on the speed of operation, the edge relationship between busy and scrub is programmable via the sequence described in figure 6a. the effective error rate is a functi on of the intrinsic rate and the environment. as a result, some users may desire an increased scrub rate to lower the error rate at the sacrifice of reduced total throughput, while others may desire a lower scrub rate to mbe scrub busy i/o mode mode h h h read uncorrectable multiple bit error l h h read valid data out x h h x device ready x h l x device ready / scrub request pending x l x not accessible device busy
4 increase the total throughput and accept a higher error rate. this rate at which the sram controlle r will correct errors from the memory is user programmable. the required sequence is described in figure 6a. a master mode scrub cycle will occur at the user defined scrub rate period. a scrub cycle is defined as the verification and correction (if necessary) of data for a single word address location. address locations are scrubbed sequentially every scrub rate period (t scrt ). scrub cycles will occur at every scrub rate period regardless of the status of control pins. control pin function will be returned upon deassertion of busy pin. the slave mode scrub cycle occurs anytime the scrub pin is asserted. the scrub cycle is defined the same as the master mode, and will occur regardless of control pin status. control pin function will be returned upon scrub deassertion. data is not only corrected duri ng the internal scrub, but again during a user requested read cycl e. if the data presented con- tains two or more errors after t avav is satisfied, the mbe signal will be asserted. (note: reading un-initialized memory locations may result in un-intended mbe assertions.) operational environment the ut8er512k32 sram incorpor ates special design, layout, and process features which a llows operation in a limited environment. table 3. operational enviro nment design specifications 1 notes: 1. the sram is immune to latchup to particles >111mev-cm 2 /mg. 2. 90% worst case particle environmen t, geosynchronous orbit, 100 mils of aluminum and default edac scrub rate. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . power-up requirements during power-up of the ut8er512k32 device, the power supply voltages will transverse through voltage ranges where the device is not guaranteed to operate before reaching final levels. since some circuits on the device will start to operate at lower voltage levels than others, the device may power-up in an unknown state. to eliminate this with most power-up situations, the device employs an on-chip power-on-reset (por) circuit. the por, however, requires time to complete the operation. therefore, it is recommended that all device activity be delayed by a minimum of 100ms, after both v dd1 and v dd2 supplies have reached their respectiv e minimum operating voltage. total dose 100k rad(si) heavy ion error rate 2 6.0x10 -16 errors/bit-day
5 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limit s indicated in the operationa l sections of this specific ation is not recommended. exposure to absolu te maximum rating conditions for extended periods may af fect device reliability and performance. 2. per mil-std-883, method 1012, section 3.4.1, p d = (t jc (max) - tc (max)) jc recommended operating conditions symbol parameter limits v dd1 dc supply voltage (core) -0.3 to 2.1v v dd2 dc supply voltage (i/o) -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d 2 maximum package power dissipation permitted @ tc = +125 o c 5w t j maximum junction temperature +150 c jc thermal resistance, junction-to-case 2 5 c/w i i dc input current 10 ma symbol parameter limits v dd1 dc supply voltage (core) 1.7 to 1.9v 1 v dd2 dc supply voltage (i/o) 3.0 to 3.6v t c case temperature range (c) screening: -55 to +125 c (w) screening: -40 to +125 c v in dc input voltage 0v to v dd2 notes: 1. for increased noise im munity, supply voltage v dd1 can be increased to 2.0v. all characteristics contai ned herein are guaranteed by characterization at v dd1 = 2.0vdc unless otherwise specified.
6 dc electrical characteristics (pre and post-radiation)* (tc = -55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening) (v dd1 = 1.7v to 1.9v; v dd2 = 3.0v to 3.6v) symbol parameter condition min max unit v ih high-level input voltage 0.7*v dd2 v v il low-level input voltage 0.3*v dd2 v v ol 1 low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) 0.2*v dd2 v v oh high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) 0.8*v dd2 v c in 2 input capacitance ? = 1mhz @ 0v 12 pf c io 2 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd2 and v ss -2 2 a i oz 3 three-state output leakage current v o = v dd2 and v ss v dd2 = v dd2 (max), g = v dd2 (max) -2 2 a i os 4, 5 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -100 +100 ma i dd1 (op 1 6,7,8 ) v dd1 supply current operating @ 1mhz, edac enabled @ default scrub rate period (see table 4). inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) -55 o c and 25 o c 25 ma v dd1 = 2.0v 125 o c 70 ma v dd1 = 1.9v 65 ma i dd1 (op 2 6,7,8 ) v dd1 supply current operating @ 50mhz, edac enabled @ default scrub rate period (see table 4). inputs: v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) -55 o c and 25 o c 250 ma v dd1 = 2.0v 125 o c 300 ma v dd1 = 1.9v 270 ma i dd2 (op 1 6,8 ) v dd2 supply current operating @ 1mhz, edac enabled @ default scrub rate period (see table 4). inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 2ma i dd2 (op 2 6,8 ) v dd2 supply current operating @ 50mhz, edac enabled @ default scrub rate period (see table 4). inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 5ma
7 notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 5e4 to 1e5 krads(si) 1. the scrub and busy pins for ut8er512k32m (master) are te sted functionally fo r vol specification. 2. measured only for initial qu alification and after process or design changes that could af fect input/output capacitance. 3. the scrub and busy pins for ut8er512k32m (master) are guaranteed by design, but neither tested nor characterized. 4. supplied as a design limit but not guaranteed or tested. 5. not more than one output may be shorted at a time for maximum duration of one second. 6. edac enabled. default scrub rate peri od applicable to master device only. 7. post radiation limits are the 125 o c temperature limit when specified. 8. operating current limit includes standby current. 9. v ih = v dd2 (max), v il = 0v. symbol parameter condition min max unit i dd1 (sb) 7,9 supply current standby @ 0hz, edac bypassed cmos inputs, i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) -55 o c and 25 o c 25 ma 125 o c 70 ma i dd2 (sb) 9 supply current standby @ 0hz, edac bypassed cmos inputs, i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) 2ma i dd1 (sb) 7,9 supply current standby a(16:0) @ 50mhz, edac bypassed cmos inputs, i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) -55 o c and 25 o c 25 ma 125 o c 70 ma i dd2 (sb) 9 supply current standby a(16:0) @ 50mhz, edac bypassed cmos inputs, i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) 2ma
8 ac characteristics read cycle (pre and post-radiation)* (tc = -55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = 1.7v to 1.9v, v dd2 = 3.0v to 3.6v) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. guaranteed by characterization, but not tested. 2. three-state is defined as a 300mv ch ange from steady-state output voltage. 3. the et (enable true) notation refe rs to the latter falling edge of e1 or rising edge of e2. 4. the ef (enable false) notation refe rs to the latter rising edge of e1 or falling edge of e2. symbol parameter unit figure min max t avav 1 1 read cycle time 20 ns 3a t av q v 1 address to data valid from address change 20 ns 3c t axqx 2 output hold time 3 ns 3a t glqx 1,2 g -controlled output enable time 2 ns 3c t glqv g -controlled output data valid 8 ns 3c t ghqz1 2 g -controlled output three-state time 2 6 ns 3c t etqx 2,3 e-controlled output enable time 5 ns 3b t etqv 3 e-controlled access time 20 ns 3b t efqz 2,4 e-controlled output three-state time 2 2 7 ns 3b t av m v address to error flag valid 20 ns 3a t axmx 2 address to error flag hold tim e from address change 3 ns 3a t glmx 2 g -controlled error flag enable time 2 ns 3c t glmv g -controlled error flag valid 7 ns 3c t etmx 2 e-controlled error fl ag enable time 5 ns 3b t etmv 3 e-controlled error flag time 20 ns 3b t ghmz 2 g-controlled error flag three-state time 2 6 ns 3b
9 a(18:0) latter of e1 low, and e2 high data valid t efqz t etqv , t etmv t etqx , t etmx dq(31:0) data valid mbe figure 3b. sram read cycl e 2: chip enable access assumptions: 1. g < v il (max) and w > v ih (min) 2. scrub > v oh (min) 3. reading uninitialized addresses will cause mbe to be asserted. assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) 2. scrub > v oh (min) 3. reading uninitialized addresses will cause mbe to be asserted. a(18:0) dq(31:0) figure 3a. sram read cycle 1: address access t avav1 t avqv1 , t avmv t axqx , t axmx previous valid data valid data valid data mbe figure 3c. sram read cycl e 3: output enable access a(18:0) mbe g assumptions: 1. e1 < v il (max), e2 and w > v ih (min) 2. scrub > v oh (min) 3. reading uninitialized addresses will cause mbe to be asserted. t glmv t glmx t avqv1 t av m v data valid dq(31:0) t glqx1 t ghqz1 t glqv data valid t ghmz
10 ac characteristics write cycle (pre and post-radiation)* (tc = -55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = 1.7v to 1.9v, v dd2 = 3.0v to 3.6v) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. tested with g high. 2. three-state is defined as 300mv ch ange from steady-state output voltage. symbol parameter min max unit figure t avav 2 1 write cycle time 10 ns 4a/4b t etwh device enable to end of write 10 ns 4a t av e t address setup time for write (e1 /e2- controlled) 0 ns 4b t av w l address setup time for write (w - controlled) 0 ns 4a t wlwh 1 write pulse width 8 ns 4a t whax address hold time for write (w - controlled) 0 ns 4a t efax address hold time for device enable (e1 /e2- controlled) 0 ns 4b t wlqz 2 w - controlled three-state time 7 ns 4a/4b t whqx 2 w - controlled output enable time 3 ns 4a t etef device enable pulse width (e1/ e2 - controlled) 10 ns 4b t dvwh data setup time 5 ns 4a t whdx data hold time 2 ns 4a t wlef 1 device enable controlled write pulse width 8 ns 4b t dvef data setup time 5 ns 4a/4b t efdx data hold time 2 ns 4b t av w h address valid to end of write 10 ns 4a t whwl 1 write disable time 1 ns 4a
11 assumptions: 1. g < v il (max). (if g > v ih (min) then q(31:0) an d mbe will be in three- state for the entire cycle.) 2. scrub > v oh (min) w t avwl figure 4a. sram write cycle 1: w - controlled access a(18:0) q(31:0) e1 t avav2 d(31:0) applied data t dvwh, t dvef t whdx t etwh, t wlef t wlwh t whax t whqx t wlqz t avwh t whwl e2
12 t efdx assumptions & notes: 1. g < v il (max). (if g > v ih (min) then q(31:0) and mbe will be in three-state for the entire cycle.) 2. either e1 / e2 scenario can occur. 3. scrub > v oh (min) a(18:0) figure 4b. sram write cycle 2: enable - controlled access w e1 d(31:0) applied data e1 q(31:0) t etef t wlef t dvef t avav2 t avet t avet t efax t efax or e2 e2
13 table 4: edac programmi ng configuration table addr bit parameter value function a (0 - 3) scrub rate period 1,2,3 3-15 note: 0-2 reserved as scrub rate period changes from 0 - 15, then the interval between scrub cycles w ill change as follows: 3 = 600 ns 8 = 13.0 us 12 = 205 us 4 = 1000 ns 9 = 25.8 us 13 = 409.8 us 4 5 = 1800 ns 10 = 51.4 us 14 = 819.4 us 4 6 = 3400 ns 11 = 102.6 us 15 = 1.64 ms 4 7 = 6600 ns a (4 - 7) busy to scrub 1,3,5 0-15 if busy changes from 0 - 15, then the interval t blsl between scrub and busy will ch ange as follows: 0 = 0 ns 6 = 300 ns 11 = 550 ns 1 = 50 ns 7 = 350 ns 12 = 600 ns 2 = 100 ns 8 = 400 ns 13 = 650 ns 3 = 150 ns 9 = 450 ns 14 = 700 ns 4 = 200 ns 10 = 500 ns 15 = 750 ns 5 = 250ns a (8) bypass edac bit 6 0, 1 if 0, then normal e dac operation will occur. if 1, then edac will be bypassed. a (9) read / write control register 0, 1 0 = a0 to a8 will be written to the control register 1 = control register will be asserted to the data bus notes: 1. values based on minimum specifications. fo r guaranteed ranges of scrub rate period (t scrt ) and busy to scrub (t blsl ), reference the master mode ac characteristic table. 2. default scrub rate period is 6600 ns. 3. scrub rate period and busy to scrub applicable to the ut8er512k32m device only. 4. period below test capability. 5. the default for t blsl is 500 ns. 6. the default state for a8 is 0. figure 5. edac control register a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 scrub rate period (default = 7h) busy to scrub (default = ah) edac bypass (default = 0h) r e a d / w rite c o n tro l r e g is te r n o te: 1. see table 4 for control register definitions
14 notes : * post-radiation performance guaranteed at 25 o c per mil-std-883 method 1019. 1. three-state is defined as 300mv change from steady-state output. 2. guaranteed by design neith er tested or characterized. edac control register ac characteristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = 1.7v to 1.9v, v dd2 = 3.0v to 3.6v symbol parameter unit figure min max t avav 3 address valid to address valid for control register cycle 200 ns 6a t av c l address valid to control low 200 ns 6a t av e x address valid to enable valid 200 ns 6a t avqv3 address to data valid control register read 400 ns 6a t mlqx 1 mbe control edac disable time 3 ns 6a t ghqz3 1 output tri-state time 2 9 ns 6a t mlgl 2 mbe low to output enable 85 ns 6a note: 1. mbe is driven high by the user. 2. lower 9 bits of the last address are used to read or config ure the control register (ref control register write/read cycles page 4 and table 4). addr (18:0) e1 low, and e2 high g t avcl t avav3 mbe 1 figure 6a. edac control register cycle assumptions: 1. scrub > v oh before the start of the configuration cycle. ignore scrub during configuration cycle. 70000h 7ff00h 3a500h 55a00h 10500h 00xyzh t avex t mlqx t avqv3 control reg. read dq (31:0) t ghqz3 t mlgl
15 master mode ac characteristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = 1.7v to 1.9v, v dd2 = 3.0v to 3.6v notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 5e4 to 1e5 krads(si) 1. see table 4 for user programmable inform ation. the value "n" is decimal equivalent of hexidecimal value 0x0 through 0xf prog rammed into control register address bits a 4 -a 7 by user. default value "n" = 10. 2. see table 4 for user programmable inform ation. the value "n" is decimal equivalent of hexidecimal value 0x3 through 0xf prog rammed into control register address bits a 0 -a 3 . default value is "n" = 7. symbol parameter min max unit figure t blsl 1 user programmable - busy low to scrub (50)(n) (90)(n)+1 ns 6b t slsh1 scrub low to scrub high 200 350 ns 6b t shbh scrub high to busy high 50 85 ns 6b t scrt 2 scrub rate period (2 n )(50)+200 (2 n )(90)+350 ns figure 6b. master mode scrub cycle scrub busy t slsh1 assumptions: 1. the conditions pertain to both a read or write. t blsl t shbh slave mode ac characteristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) symbol parameter min max unit figure t slsh2 scrub low to scrub high (slave) 200 ns 6c t shsl 1 scrub high to scrub low (slave) 400 ns 6c scrub t slsh2 figure 6c. slave mode scrub cycle assumptions: 1. the conditions pertain to both a read or write. notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 5e4 to 1e5 krads(si) 1. guaranteed by design, neither tested nor characterized. t shsl
16 90% cmos input pulses 10% < 2ns < 2ns v ss v dd2 10% 90% figure 7. ac test loads and input waveforms notes: 1. measurement of data output occurs at the low to high or high to low tr ansition mid-point (i.e., cmos input = v dd2 /2 v dd2 dut zo = 50-ohms v dd2 c l = 40pf r term 100-ohms test point r term 100-ohms
17 packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in ac cordance with mil-prf-38535. figure 8. 68-lead ceramic quad flatpack
18 ordering information 512k x 32 sram ut **** ** - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = hirel temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) package type: (w) = 68-lead ceramic quad flatpack access time: (21) = 20ns read / 10ns write access times device type: (8er512k32m) =512k x 32 sram master device (8er512k32s) = 512k x 32 sram slave device notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per aeroflex colorado spring s manufacturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed. 5. extended industrial temperature flow per aeroflex colorado springs manufacturing fl ows document. devices are tested at -40 c, room temp, and 125 c. radiation neither tested nor guaranteed.
19 512k x 32 sram: smd 5962 - ******* ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 68-lead ceramic quad flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 20ns read / 10ns write master device (-55 c to +125 c) (02) = 20ns read / 10ns write master device (-40 c to +125 c) (03) = 20ns read / 10ns write slave device (-55 c to +125 c) (04) = 20ns read / 10ns write slave device (-40 c to +125 c) drawing number: 06261 total dose: (r ) = 100 krad(si) federal stock class designator: no options ** * notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold).
20 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hirel

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